View PCS2P5T907A_4647966.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

September 2006 rev 0.2 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
PCS2P5T907A
Features
* * * * * * * * * * * * Guaranteed Low Skew < 25pS (max) Very low duty cycle distortion High speed propagation delay < 2.5nS. (max) Up to 250MHz operation Very low CMOS power levels 1.5V VDDQ for HSTL interface Hot Insertable and over-voltage tolerant inputs 3-level inputs for selectable interface Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface Selectable differential or single-ended inputs and ten single ended outputs 2.5V Supply Voltage Available in TSSOP Package
Functional Description
The PCS2P5T907A 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to ten single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The PCS2P5T907A can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The PCS2P5T907A has two output banks that can be asynchronously enabled/ disabled. Multiple power and grounds reduce noise.
Applications:
PCS2P5T907A is targeted towards Clock and signal distribution applications.
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.2
Block Diagram
PCS2P5T907A
TxS GL G OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL RxS A A/VREF OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL Q5 OUTPUT CONTROL Q1
Q2
Q3
Q4
G2
Q6
Q7
Q8
Q9
Q10
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
2 of 21
September 2006 rev 0.2
Pin Configuration
PCS2P5T907A
GL VDD VDD GND GND G1 VDDQ Q2 Q1 GND VDDQ A/VREF A VDDQ GND Q10 Q9 VDDQ G2 GND GND VDD VDD RxS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40
GND VDDQ VDDQ GND GND GND VDDQ Q3 Q4 GND VDDQ Q5 Q6 VDDQ GND Q7 Q8 VDDQ VDDQ GND GND VDDQ GND TxS
PCS2P5T907A
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
3 of 21
September 2006 rev 0.2
Pin Description1 Symbol
A
PCS2P5T907A
I/O
I
Type
Adjustable1
Description
Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input. Complementary clock input. A/VREF is the "complementary" side of A if the input is in differential mode. If operating in single-ended mode, A/VREF is connected to GND. For single-ended operation in differential mode, A/VREF should be set to the desired toggle voltage for A: 2.5V LVTTL VREF= 1250mV 1.8V LVTTL, eHSTL VREF= 900mV HSTL VREF= 750mV LVEPECL VREF= 1082mV Gate for outputs Q1 through Q5. When G1 is LOW, these outputs are enabled. When G1 is HIGH, these outputs are asynchronously disabled to the level designated by GL4. Gate for outputs Q6 through Q10. When G2 is LOW, these outputs are enabled. When G2 4 is HIGH, these outputs are asynchronously disabled to the level designated by GL . Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW. Clock outputs Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential (LOW) clock input Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in conjunction with VDDQ to set the interface levels. Power supply for the device core and inputs Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, VDDQ should be connected to VDD. Power supply return for all power
A / VREF
I
Adjustable1
G1 G2 GL Qn RxS TxS VDD VDDQ GND
I I I O I I I I
LVTTL
5
LVTTL5 LVTTL5 Adjustable2 3 Level3 3 Level3 PWR PWR PWR
NOTES: 1. Inputs are capable of translating the following interface standards. User can select between: Single-ended 2.5V LVTTL levels or Differential 2.5V/1.8V LVTTL levels Single-ended 1.8V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL levels 2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage. 3. 3 level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant. 4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
Absolute Maximum Ratings1 Symbol
VDD VDDQ VI VO VREF TSTG TJ Power Supply Voltage2 Output Power Supply2 Input Voltage Output Voltage3 Reference Voltage3 Storage Temperature Junction Temperature
Description
Max
-0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 -0.5 to VDDQ +0.5 -0.5 to +3.6 -65 to +165 150
Unit
V V V V V C C
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met. 3. Not to exceed 3.6V.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
4 of 21
September 2006 rev 0.2
Capacitance1 (TA = +25C, F = 1.0MHz) Symbol Parameter
CIN Input Capacitance
PCS2P5T907A
Min Typ
3.5
Max
Unit
pF
NOTE: 1. This parameter is measured at characterization but not tested. Capacitance applies to all inputs except RxS and TxS.
Recommended Operating Range Symbol
TA 1 VDD VDDQ1 VT
Description
Ambient Operating Temperature Internal Power Supply Voltage HSTL Output Power Supply Voltage Extended HSTL and 1.8V LVTTL Output Power Supply Voltage 2.5V LVTTL Output Power Supply Voltage Termination Voltage
Min
-40 2.4 1.4 1.65
Typ
+25 2.5 1.5 1.8 VDD VDDQ/ 2
Max
+85 2.6 1.6 1.95
Unit
C V V V V V
NOTE: 1. All power supplies should operate in tandem; if VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at a maximum, and vice-versa.
Input/Output Selection1 Input
2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 1.8V LVTTL 2.5V LVTTL
Output
Input
2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF
Output
eHSTL
HSTL
NOTE: 1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single- ended mode require the A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode,
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
5 of 21
September 2006 rev 0.2
requiring a VREF. Differential (DIF) inputs are used only in differential mode.
PCS2P5T907A
DC Electrical Characteristics Over Operating Range Symbol
VIHH VIMM VILL I3
Parameter
Input HIGH Voltage Level1 Input MID Voltage Level
1
Test Conditions
3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN= VDD VIN= VDD/2 VIN= GND HIGH Level MID Level LOW Level
Min
VDD- 0.4 VDD/2 - 0.2
Max
VDD/2 + 0.2 0.4 200
Unit
V V V A
Input LOW Voltage Level1 3-Level Input DC Current (RxS, TxS)
-50 -200
+50
NOTE: 1. These inputs are normally wired to VDD, GND, or left floating. Internal temination resistors bias unconnected inputs to VDD/2.
DC Electrical Characteristics Over Operating Range for HSTL1 Symbol
IIH IIL VIK VIN VDIF VCM VIH VIL VREF
Parameter
Input HIGH Current9 Input LOW Current9 Clamp Diode Voltage DC Input Voltage DC Differential Voltage DC Common Mode Input 3,8 Voltage DC Input HIGH4,5,8 DC Input LOW Single-Ended Reference 4,8 Voltage Output HIGH Voltage Output LOW Voltage
4,6,8 2,8
Test Conditions
VDD= 2.6V VDD= 2.6V VI = VDDQ/GND VI = GND/VDDQ
Min
Typ7
Max
5 5
Unit
A V V V mV mV mV mV V V
Input Characteristics
VDD= 2.4V, IIN= -18mA -0.3 0.2 680 VREF+100
-0.7
- 1.2 +3.6
750
900 VREF-100
750 IOH= -8mA IOH= -100A IOL= 8mA IOL= 100A VDDQ- 0.4 VDDQ- 0.1
-
Output Characteristics
VOH VOL
0.4 0.1
V V
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
6 of 21
September 2006 rev 0.2
Power Supply Characteristics for HSTL Outputs1 Symbol
IDDQ IDDQQ IDDD IDDDQ
PCS2P5T907A
Parameter
Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current
Test Conditions2
VDDQ= Max., Reference Clock = LOW Outputs enabled, All outputs unloaded VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDD= Max., VDDQ= Max., CL= 0pF VDD= Max., VDDQ= Max., CL= 0pF VDDQ= 1.5V, FREFERENCE CLOCK CL= 15pF VDDQ= 1.5V, FREFERENCE CLOCK CL= 15pF VDDQ= 1.5V, FREFERENCE CLOCK CL= 15pF VDDQ= 1.5V, FREFERENCE CLOCK CL= 15pF =100MHz, =250MHz, =100MHz, =250MHz,
3
Typ
20 0.1 20 30 20 35 35 50
Max
30 0.3 30 50 40
Unit
mA mA A/MHz A/MHz
ITOT
mA 50 70 mA 100
ITOTQ
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for HSTL Symbol
VDIF VX VTHI tR, tF Input Signal Swing1 Differential Input Signal Crossing Point Input Signal Edge Rate4
2 3
Parameter
Value
1 750 Crossing Point 1
Units
V mV V V/nS
Input Timing Measurement Reference Level
NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
7 of 21
September 2006 rev 0.2
DC Electrical Characteristics Over Operating Range for eHSTL1 Symbol Parameter Input Characteristics
IIH IIL VIK VIN VDIF VCM VIH VIL VREF Input HIGH Current9 Input LOW Current9 Clamp Diode Voltage DC Input Voltage DC Differential Voltage DC Common Mode Input Voltage3,8 DC Input HIGH4,5,8 DC Input LOW Single-Ended Reference Voltage4,8 Output HIGH Voltage Output LOW Voltage IOH= -8mA IOH= -100A IOL= 8mA IOL= 100A VDDQ- 0.4 VDDQ- 0.1
4,6,8 2,8
PCS2P5T907A
Test Conditions
VDD= 2.6V VI = VDDQ/GND VDD= 2.6V VI = GND/VDDQ VDD= 2.4V, IIN = -18mA
Min
Typ7
Max
5 5
Unit
A V V V mV mV mV mV V V
- 0.7 -0.3 0.2 800 VREF+ 100 900 900
- 1.2 +3.6 1000 VREF-100 -
Output Characteristics
VOH VOL
0.4 0.1
V V
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in a differential mode, A / VREF is tied to the DC voltage VREF. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 9. For differential mode (RxS = LOW), A and A / VREF must be at the opposite rail.
Power Supply Characteristics for eHSTL Outputs1 Symbol
IDDQ IDDQQ IDDD IDDDQ ITOT
Parameter
Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current
Test Conditions2
VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded 3 VDDQ= Max., Reference Clock = LOW Outputs enabled, All outputs unloaded VDD= Max., VDDQ= Max., CL= 0pF VDD= Max., VDDQ= Max., CL= 0pF VDDQ= 1.8V, FREFERENCE CLOCK = 100MHz, CL= 15pF VDDQ= 1.8V, FREFERENCE CLOCK = 250MHz, CL= 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL= 15pF VDDQ= 1.8V, FREFERENCE CLOCK = 250MHz, CL= 15pF
Typ
20 0.1 20 40 20 35 40 80
Max
30 0.3 30 60 40
Unit
mA mA A/MHz A/MHz mA
50 80 mA 160
ITOTQ
Total Power VDDQ Supply Current
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
8 of 21
September 2006 rev 0.2
Differential Input AC Test Conditions for eHSTL Symbol
VDIF VX VTHI tR, tF Input Signal Swing1 Differential Input Signal Crossing Point Input Signal Edge Rate4
2 3
PCS2P5T907A
Parameter
Value
1 900 Crossing Point 1
Units
V mV V V/nS
Input Timing Measurement Reference Level
NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics Over Operating Range for LVEPECL1 Symbol Parameter Input Characteristics
IIH IIL VIK VIN VCM VREF VIH VIL Input HIGH Current6 Input LOW Current6 Clamp Diode Voltage DC Input Voltage DC Common Mode Input 3,5 Voltage Single-Ended Reference Voltage4,5 DC Input HIGH DC Input LOW
Test Conditions
VDD= 2.6V VDD= 2.6V VI = VDDQ/GND VI = GND/VDDQ
Min
Typ2
Max
5 5
Unit
A V V mV mV
VDD= 2.4V, IIN = -18mA - 0.3 915
-0.7 1082 1082 1275 555
- 1.2 3.6 1248
1620 875
mV mV
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Typical values are at VDD = 2.5V, +25C ambient. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation while in differential mode, A/VREF is tied to the DC voltage VREF. 5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Differential Input AC Test Conditions for LVEPECL Symbol
VDIF VX VTHI tR, tF Input Signal Swing
1 2 3
Parameter
Differential Input Signal Crossing Point
4
Value
732 1082 Crossing Point 1
Units
mV mV V V/nS
Input Timing Measurement Reference Level Input Signal Edge Rate
NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
9 of 21
September 2006 rev 0.2
DC Electrical Characteristics Over Operating Range for 2.5V LVTTL1 Symbol Parameter Input Characteristics
IIH IIL VIK VIN VIH VIL VDIF VCM VIH VIL VREF Input HIGH Current10 Input LOW Current10 Clamp Diode Voltage DC Input Voltage DC Input HIGH DC Input LOW DC Differential Voltage3,9 DC Common Mode Input 4,9 Voltage DC Input HIGH5,6,9 DC Input LOW5,7,9 Single-Ended Reference 5,9 Voltage Output HIGH Voltage Output LOW Voltage IOH= -12mA IOH= -100A IOL= 12mA IOL= 100A VDDQ- 0.4 VDDQ- 0.1
PCS2P5T907A
Test Conditions
VDD= 2.6V VDD= 2.6V VI = VDDQ/GND VI = GND/VDDQ
Min.
Typ8
Max
5 5
Unit
A V V V V V
VDD= 2.4V, IIN = -18mA -0.3 1.7
- 0.7
- 1.2 +3.6
Single-Ended Inputs2
0.7 0.2 1150 VREF+ 100 VREF-100 1250 1250 1350
Differential Inputs
mV mV mV mV
Output Characteristics
VOH VOL V V 0.4 0.1 V V
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
10 of 21
September 2006 rev 0.2
Power Supply Characteristics for 2.5V LVTTL Outputs1 Symbol
IDDQ IDDQQ IDDD IDDDQ
PCS2P5T907A
Parameter
Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current
Test Conditions2
VDDQ= Max., Reference Clock = LOW Outputs enabled, All outputs unloaded VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDD= Max., VDDQ= Max., CL= 0pF VDD= Max., VDDQ= Max., CL= 0pF VDDQ= 2.5V, FREFERENCE CLOCK= 100MHz, CL= 15pF VDDQ= 2.5V, FREFERENCE CLOCK= 200MHz, CL= 15pF VDDQ= 2.5V, FREFERENCE CLOCK= 100MHz, CL= 15pF VDDQ= 2.5V, FREFERENCE CLOCK= 200MHz, CL= 15pF
3
Typ
20 0.1 25 40 25 40 40 100
Max
30 0.3 40 70 40
Unit
mA mA A/MHz A/MHz
ITOT
mA 70 80 mA 200
ITOTQ
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for 2.5V LVTTL Symbol
VDIF VX VTHI tR, tF Input Signal Swing1 Differential Input Signal Crossing Point Input Signal Edge Rate
4 2 3
Parameter
Value
VDD VDD/2 Crossing Point 2.5
Units
V V V V/nS
Input Timing Measurement Reference Level
NOTES: 1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2.5V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
Single-Ended Input AC Test Conditions for 2.5V LVTTL Symbol
VIH VIL VTHI tR, tF Input HIGH Voltage Input LOW Voltage Input Timing Measurement Reference Level1 Input Signal Edge Rate2
Parameter
Value
VDD 0 VDD/2 2
Units
V V V V/nS
NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
11 of 21
September 2006 rev 0.2
DC Electrical Characteristics Over Operating Range for 1.8V LVTTL1 Symbol
IIH IIL VIK VIN VIH VIL VDIF VCM VIH VIL VREF
PCS2P5T907A
Parameter
Input HIGH Current12 Input LOW Current12 Clamp Diode Voltage DC Input Voltage DC Input HIGH DC Input LOW DC Differential Voltage3,9 DC Common Mode Input 4,9 Voltage DC Input HIGH5,6,9
Test Conditions
VDD= 2.6V VI = VDDQ/GND VDD= 2.6V VI = GND/VDDQ VDD= 2.4V, IIN= -18mA
Min
Typ8
Max
5 5
Unit
A V V V V V
Input Characteristics
-0.7 - 0.3 1.07310
- 1.2 VDDQ+ 0.3
Single-Ended Inputs2
0.683 0.2 825 VREF+ 100 900 975
11
Differential Inputs
mV mV mV mV
DC Input LOW5,7,9 Single-Ended Reference Voltage5,9 Output HIGH Voltage Output LOW Voltage IOH= -6mA IOH= -100A IOL= 6mA IOL= 100A VDDQ- 0.4 VDDQ- 0.1
VREF- 100 900
Output Characteristics
VOH VOL V V 0.4 0.1 V V
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within 200mV of VREF when VREF is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply. 11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply. 12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
12 of 21
September 2006 rev 0.2
Power Supply Characteristics for 1.8V LVTTL Outputs1 Symbol
IDDQ IDDQQ IDDD IDDDQ
PCS2P5T907A
Parameter
Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current
Test Conditions2
VDDQ= Max., Reference Clock = LOW Outputs enabled, All outputs unloaded VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDD= Max., VDDQ= Max., CL= 0pF VDD= Max., VDDQ= Max., CL= 0pF VDDQ= 1.8V, FREFERENCE CLOCK= 100MHz, CL= 15pF VDDQ= 1.8V, FREFERENCE CLOCK= 200MHz, CL= 15pF VDDQ= 1.8V, FREFERENCE CLOCK= 100MHz, CL= 15pF VDDQ= 1.8V, FREFERENCE CLOCK= 200MHz, CL= 15pF
3
Typ
20 0.1 20 55 25 40 55 130
Max
30 0.3 40 80 40
Unit
mA mA A/MHz A/MHz
ITOT
mA 60 110 mA 260
ITOTQ
Total Power VDDQ Supply Current
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for 1.8V LVTTL Symbol
VDIF VX VTHI tR, tF Input Signal Swing1 Differential Input Signal Crossing Point Input Signal Edge Rate
4 2
Parameter
Value
VDDI VDDI /2 Crossing Point 1.8
Units
V mV V V/nS
Input Timing Measurement Reference Level3
NOTES: 1. VDDI is the nominal 1.8V supply (1.8V 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1.8V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
Single-Ended Input AC Test Conditions for 1.8V LVTTL Symbol
VIH VIL VTHI tR, tF
Parameter
Input HIGH Voltage1 Input LOW Voltage Input Timing Measurement Reference Level2 Input Signal Edge Rate3
Value
VDDI 0 VDDI /2 2
Units
V V mV V/nS
NOTES: 1. VDDI is the nominal 1.8V supply (1.8V 0.15V) of the part or source driving the input. 2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 3. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
13 of 21
September 2006 rev 0.2
AC Electrical Characteristics Over Operating Range7 Symbol Skew Parameters
tSK(O)
PCS2P5T907A
Parameter
Single-Ended and Differential Modes Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes Single-Ended in Differential Mode (DSE)
Min
Typ
Max
25
Unit
Same Device Output Pin-toPin Skew1
pS 25 300 pS 300 350 pS 350 40 60 300 pS 300 %
tSK(P)2
Pulse Skew3
tSK(P)4 dT5 tSK(PP)
Pulse Skew3 Duty Cycle Part-to-Part Skew6
Single-Ended and Differential Modes Single-Ended in Differential Mode (DSE)
Propagation Delay
tPLH tPHL tR tF fO Propagation Delay A to Qn Output Rise Time (20% to 80%) Output Fall Time (20% to 80%) 2.5V/1.8V LVTTL Outputs HSTL / eHSTL Outputs 2.5V/1.8V LVTTL Outputs HSTL / eHSTL Outputs 350 350 350 350 2.5 1050 1350 1050 1350 250 200 3.5 3 nS pS pS MHz
Frequency Range (HSTL/eHSTL outputs) Frequency Range (2.5V/1.8V LVTTL outputs) Output Gate Enable to Qn Output Gate Enable to Qn Driven to GL Designated Level
Output Gate Enable/Disable Delay
tPGE tPGD nS nS
NOTES: 1. Skew measured between all outputs under identical input and output interfaces, transitions, and load conditions on any one device. 2. For 1.8V LVTTL and eHSTL outputs only. 3. Skew measured is difference between propagation times tPLH and tPHL of any output under identical input and output interfaces, transitions, and load conditions on any one device. 4. For 2.5V LVTTL outputs only. 5. For HSTL outputs only. 6. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD/VDDQ levels and temperature. 7. Guaranteed by design.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
14 of 21
September 2006 rev 0.2
AC Differential Input Specifications1 Symbol
tW
PCS2P5T907A
Parameter
Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)2 Reference Clock Pulse Width HIGH or LOW 2 (2.5V / 1.8V LVTTL outputs) AC Differential Voltage3 AC Input HIGH4,5 AC Input LOW
4,6
Min
1.73
Typ
Max
Unit
nS
2.17 400 Vx + 200 Vx - 200 mV mV mV mV mV 875 mV
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF VIH VIL
LVEPECL
VDIF VIH VIL AC Differential Voltage AC Input HIGH
4 3
400 1275
AC Input LOW4
NOTES: 1. For differential input mode, RxS is tied to GND. 2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined by VDIF has been met or exceeded. 3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state. 4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range. 5. Voltage required to switch to a logic HIGH, single-ended operation only. 6. Voltage required to switch to a logic LOW, single-ended operation only.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
15 of 21
September 2006 rev 0.2
PCS2P5T907A
AC Timing Waveforms
Propagation and Skew Waveforms
NOTES: 1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO. 2. Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse.
Gate Disable/Enable Showing Runt Pulse Generation
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
16 of 21
September 2006 rev 0.2
PCS2P5T907A
Test Circuits and Conditions
Test Circuit for Differential Input1 Differential Input Test Conditions Symbol
R1 R2 VDDI 100 100 VCM*2 HSTL: Crossing of A and A eHSTL: Crossing of A and A LVEPECL: Crossing of A and A 1.8V LVTTL: VDDI/2 2.5V LVTTL: VDD/2
VDD= 2.5V 0.1V
Unit
V
VTHI
V
NOTE: 1. This input configuration is used for all input interfaces. For single-ended testing, the VIN input is tied to GND. For testing single-ended in differential input mode, the VIN is left floating.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
17 of 21
September 2006 rev 0.2
PCS2P5T907A
Test Circuit for SDR Outputs
SDR Output Test Conditions VDD= 2.5V 0.1V VDDQ= Interface Specified
15 100 100 VDDQ/ 2
Symbol
CL R1 R2 VTHO
Unit
pF V
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
18 of 21
September 2006 rev 0.2
Package Information
PCS2P5T907A
48-lead TSSOP Package (6.10 mm Body, JEDEC MO-153-ED)
Dimensions Symbol Min
A A1 A2 b c D E1 E e L N 0 8 0.018 0.004 0.488 0.236 0.319 BSC 0.020 BSC 0.030 48 0 8 0.45 .... 0.002 0.031 0.008 BSC 0.008 0.496 0.244 0.09 12.40 6.00 8.10 BSC 0.50 BSC 0.75
Inches Max
0.047 0.006 0.041
Millimeters Min
... 0.05 0.8 0.20 BSC 0.20 12.60 6.20
Max
1.20 0.15 1.05
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
19 of 21
September 2006 rev 0.2
Ordering code Part Number
PCS2P5T907AG-48TT PCS2P5T907AG-48TR PCS2I5T907AG-48TT PCS2I5T907AG-48TR
PCS2P5T907A
Marking
2P5T907AG 2P5T907AG 2I5T907AG 2I5T907AG
Package Type
48 Pin TSSOP, Tube, Pb Free 48 Pin TSSOP, Tape and Reel, Pb Free 48 Pin TSSOP, TUBE, Pb Free 48 Pin TSSOP, Tape and Reel, Pb Free
Operating Range
Commercial Commercial Industrial Industrial
Ordering Information
PCS2P5T907AG-48TR
OR - TSOT23 -6,T/R TT - TSSOP, TUBE TR - TSSOP, T/R VT - TVSOP, TUBE VR - TVSOP, T/R ST - SOIC, TUBE AR - SSOP, T/R AT - SSOP, TUBE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X = Automotive (-40C to +125C) I = Industrial P or n/c = Commercial (-40C to +85C) (0C to +70C) 6 - power management 7 - power management 8 - power management 9 - Hi performance 0 - reserved SR QR QT BT BR UR DR DT - SOIC, T/R - QFN, T/R - QFN, TRAY - BGA, TRAY - BGA, T/R - SOT-23, T/R - QSOP, T/R - QSOP, TUBE
1 - reserved 2 - Non PLL based 3 - EMI Reduction 4 - DDR support products 5 - STD Zero Delay Buffer
PULSECORE Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
20 of 21
September 2006 rev 0.2
PCS2P5T907A
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P5T907A Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
21 of 21

▲Up To Search▲

Price & Availability of PCS2P5T907A

	To Download PCS2P5T907A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .